1. Field of the Invention
This invention relates to signaling in electronic systems, and more particularly, to methods and circuits for providing sufficient margins for received signals.
2. Description of the Related Art
As digital systems technology has advanced, data transmission rates have increased accordingly. Data transmission rates of over 1 Gb/s (gigabit per second) are commonplace in many digital system components, such as high-speed communications links digital integrated circuits. Digital signals transmitted over such high-speed communications links may be received by receiver circuits that are configured to sample received signals in order to determine their correct value (e.g., logic 0 or logic 1). Bit errors may be introduced if received signals are sampled incorrectly.
Signals transmitted over high-speed communications links may be subject to degradation that can in turn cause the signals to be sampled incorrectly. One cause of signal degradation may be jitter. Broadly speaking, jitter may be defined as timing variations in a signal resulting from phase shifts, frequency shifts, and so forth. Another cause of signal degradation may be inter-symbol interference (ISI). Broadly speaking, ISI occurs when one transmitted symbol interferes with another subsequently transmitted symbol (e.g., when a transmitted logic value interferes with the next transmitted logic value). ISI may result from impedance mismatches, reflections, and other imperfections in the signal path along which data values are transmitted.
To overcome the problems that may be introduced by jitter and ISI, various equalization techniques may be used. One such technique is known as decision feedback equalization (DFE). In implementing a receiver configured to perform DFE, the history of previous data transmissions may be considered. More particularly, for a particular signal path, a receiver using DFE may use information about bits previously transmitted on that signal line. A DFE receiver may feed back information based on received bits to compensate for ISI and jitter that may have been introduced by one or more previously received bits. Based on the compensation provided by the use of DFE, the occurrence of bit errors may be reduced, if not eliminated.